Today, modern electronic design automation (EDA) tools synthesize a netlist from a logic description developed by a system architect. The EDA tools, i.e., synthesis tools, use a library of cells as an input to decide upon the most optimum construction of the logic description based upon the system architect's constraints, such as constraints related to area, speed, or power. The library of cells is typically called a standard cell library.
The standard cell library includes of a set of logical and physical models for each cell in the library. The logical model of the cell describes the logical function of the cell to the synthesis tool. The physical model of the cell includes performance data, area information, a polygon representation of the cell, and information used by place and route tools, i.e., tools used to physically construct the design. The standard cell library can include a large number of cells for synthesizing complex logic descriptions. Most current standard cell libraries include between 500 and 1000 cells, including drive strength variants. Drive strength variants are cells that have the same logical function but have different physical characteristics such as area, power, and performance. Typically, standard cell library development is very resource intensive, wherein the resources include human and computer resources. The performance characterization and polygon layout of each cell in the standard cell library typically represent the most resource intensive development operations, wherein the performance characterization is computer resource intensive and the polygon layout is human resource intensive.
The effectiveness of the synthesis solution depends upon the richness of the standard cell library and how well the standard cell library is suited for the intended system design. Standard cells are typically constructed such that any logic cell can be placed next to any other logic cell. Thus, a general requirement is that each standard cell be constructed in accordance with a set of rules, including specifications for cell height, border or edge characteristics, and device size limitations.
While synthesis of logic descriptions into netlists can be accomplished using current standard cell libraries, a number of shortcomings are associated with the current synthesis approach. For example, a standard cell library developer may be required to satisfy differing specifications of many system designs. To satisfy the differing system design specifications, the standard cell library developer is often required to make compromises when deciding upon the contents of the standard cell library. One approach for mitigating the need to make such compromises is for the standard cell library developer to support multiple standard cell libraries, wherein each of the multiple standard cell libraries is targeted to a particular system design specification. However, support of multiple standard cell libraries is very resource intensive. For example, each standard cell library delivery involves performance characterization and polygon layout of each cell contained therein. Additionally, modern semiconductor processes usually go through several releases in which the physical aspects of the as-fabricated cells change from what is originally defined in the standard cell library. Such changes in the physical aspects of the as-fabricated cells can affect the cell performance characterization data and/or the cell polygon layout. Thus, when physical aspects of the as-fabricated cells change, the standard cell library developer will generally need to redeliver the standard cell library models with incorporation of appropriate cell physical aspect changes.